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1. Field of the Invention
The present invention relates to the field of data networking and, in particular, to a method and apparatus for increasing data rates in a data network while maintaining system coherency.
2. Background Information
As computer technology has evolved, so too has the use of data networks to communicatively couple computer systems together enabling them to communicate with one another. Data networks come in many different sizes and network topologies. From small peer-to-peer networks enabling multiple users of a small office to share data, to more formal local area networks (LAN), wide-area and global data networks (i.e., the Internet). As reliance on such computer networks has increased, so too has the data traffic and congestion experienced on such networks.
Those skilled in the art will appreciate that a lot of congestion occurs within the network devices used as network routing or switching points within the network core, e.g., routers, switches, bridges and the like. One reason for such congestion is the processing associated with the routing or switching decisions which are made, typically, on a frame by frame basis. That is, data packets are received and stored in a packet buffer(s) (e.g., system memory), analyzed and forwarded based on routing information contained within the packet, e.g., destination node address, as well as other network routing criteria, e.g., load balancing considerations. Another reason for the congestion is that many prior art input/output (I/O) busses are not optimized for network switching applications. As network traffic has increased, so too has the pressure to alleviate the bottlenecks associated with xe2x80x9ccore congestionxe2x80x9d, i.e., the congestion caused by devices in the network core.
A necessary first step in alleviating the core congestion was to increase the number and processing capability of processors in core devices, thereby creating a multiprocessor environment in the network core devices. However, those skilled in the art will appreciate that having multiple processors access common memory space dramatically increases the complexity of the data management required, often referred to as system coherency. That is, when multiple processors have access to common memory space, steps must be taken to ensure that the data retrieved from a memory space is still valid data. Accordingly, prior art network devices relied on either hardware or software approaches to maintaining system coherency for data stored within the common data packet buffers. Although the move to multiprocessing system with either hardware or software methods for maintaining system coherency incrementally improved the congestion experienced at network nodes, such improvement was short-lived. That is, traffic over data networks is constantly increasing thus requiring new and improved network devices to manage such data and alleviate congestion bottlenecks.
Thus, a method and apparatus for increasing data rates while maintaining system coherency is required, unencumbered by the deficiencies and inherent limitations commonly associated with the network devices of the prior art. It will be apparent to those skilled in the art, from the description to follow, that the present invention achieves these and other desired results.
In accordance with the teachings of the present invention, a method and apparatus for increasing data rates in a data network while maintaining system coherency is provided. In particular, in accordance with one embodiment of the present invention, an apparatus comprising system memory and a cache memory maintain system coherency for data stored in a subset of memory elements utilizing software coherency control, while system coherency for all remaining memory elements is maintained utilizing hardware coherency control.